Tile based rendering systems are well known, these subdivide an image into a plurality of rectangular blocks or tiles in order to increase efficiency of the rasterisation process.
FIG. 1 illustrates a traditional tile based rendering system. Tile based rendering systems operate in two phases, a geometry processing phase and a rasterisation phase. During the geometry processing phase a primitive/command fetch unit 100 retrieves command and primitive data from memory and passes this to a geometry fetch unit 105 which fetches the geometry data 110 from memory and passes it to a transform unit 115. This transforms the primitive and command data into screen space and applies any lighting/attribute processing as required using well-known methods. The resulting data is passed to a culling unit 120 which culls any geometry that isn't visible using well known methods. The culling unit writes any remaining geometry data to the transformed parameter buffer 135 and also passes the position data of the remaining geometry to the tiling unit 125 which generates a set of screen space objects lists for each tile which are written to the tiled geometry lists 130. Each object list contains references to the transformed primitives that exist wholly or partially in that tile. The lists exist for every tile on the screen, although some object lists may have no data in them. This process continues until all the geometry within the scene has been processed.
During the rasterisation phase the object lists are fetched by a tiled parameter fetch unit 140 which first fetches the object references and then the object data referenced and supplies them to a hidden surface removal unit (HSR) 145 which removes surfaces which will not contribute to the final scene (usually because they are obscured by another surface). The HSR unit processes each primitive in the tile and passes only data for visible primitives/pixels to a texturing and shading unit (TSU) 150. The TSU takes the data from the HSR unit and uses it to fetch textures and apply shading to each pixel within a visible object using well-known techniques. The TSU then supplies the textured and shaded data to an alpha test/fogging/alpha blending unit 155. This is able to apply degrees of transparency/opacity to the surfaces again using well-known techniques. Alpha blending is performed using an on chip tile buffer 160 thereby eliminating the requirement to access external memory for this operation. It should be noted that the TSU and alpha test/fogging/alpha blend units may be fully programmable in nature.
Once each tile has been completed, a pixel processing unit 165 performs any necessary backend processing such as packing and anti-alias filtering before writing the resulting data to a rendered scene buffer 170, ready for display.
Typically modem computer graphics applications utilise a significant amount of geometry that remains static throughout a scene or across multiple scenes, this geometry data is stored in what is commonly known as static vertex buffers that typically reside in memory that is local to the graphics processing unit. Current tile based systems transform this data into screen space and store the resulting geometry within a parameter buffer/tiled screen spaced geometry list that can consume a considerable amount of additional storage and memory bandwidth.